PhD in Smart Network-on-Chip Design for Congestion Management in 2.5D Chiplet Systems

Research theme: Computer Science

This 3.5-year PhD project is fully funded; students who are eligible to pay tuition fees at the Home rate are eligible to apply. The successful candidate will receive an annual tax-fee stipend set at the UKRI rate (£21,805 for 2026/27) and tuition fees will be paid. We expect the stipend to increase each year. The start date is January 2027.

We recommend that you apply early as the advert may be removed before the deadline.

The semiconductor industry is rapidly shifting towards modular design based on chiplets and Multi-Chip Modules, where multiple dies — CPUs, GPUs, AI accelerators, and memory stacks — are integrated side by side on a common interposer. This paradigm offers compelling advantages in cost, flexibility, and performance, but introduces a fundamental challenge: the communication fabric connecting heterogeneous chiplets must cope with highly dynamic, workload-dependent traffic while maintaining high performance and efficiently managing congestion.

This research addresses that challenge through the design of a Smart Network-on-Chip (SNoC): an asynchronous communication fabric integrating elements of intelligence into its microarchitecture. The research focuses on intelligent congestion management, replacing static routing heuristics with data-driven policies capable of adapting to changing traffic conditions, anticipating congestion, and making effective routing decisions across diverse workloads and traffic regimes. Potential research directions include the design of lightweight inference engines, the integration of learning-based policies into router microarchitectures, and the exploration of distributed intelligence for adaptive traffic management. The research is grounded in an existing RTL-verified asynchronous NoC IP, which serves as the hardware foundation for the proposed extensions.

We are looking for two motivated PhD candidates with a background in digital design, computer architecture, and/or the backend digital design flow, and an interest in the intersection of hardware design and intelligent systems. Prior experience with RTL design, system architecture simulation, and/or machine learning for hardware is a plus. The research framework outlined above is flexible and is meant to accommodate a range of specific research directions that candidates may wish to develop based on their own interests, creativity, background, and skills. What matters most is intellectual rigour and the ability to identify, within this framework, a consistent and original research idea.

Candidates with an interest in LLM-aided design methodologies and agentic approaches to hardware design are strongly encouraged to apply. A desirable research objective would be to understand how these approaches can be leveraged to automate and improve the design of intelligent NoC architectures.

Applicants should have, or expect to achieve, at least a 2.1 honours degree or a master’s (or international equivalent) in a relevant science or engineering related discipline. This position is for UK nationals only.

T apply, please contact the main supervisor, Dr. Davide Bertozzi. Please include details of your current level of study, academic background and any relevant experience and include a paragraph about your motivation to study this PhD project.